This invention relates to electronic structures such as devices, test structures and integrated circuits and, more particularly, to testing such components to measure certain characteristics thereof or to determine whether or not they contain defects.
In practice, a variety of well-known techniques are commonly utilized during or subsequent to manufacture to measure certain characteristics of devices, test structures and integrated circuits or to detect defects therein. As, however, the trend toward smaller feature sizes and faster, denser components continues, the capability of these known testing procedures is in many cases severely strained.
Often, for example, it is too time consuming, or even impossible, to perform full functional testing on a very-large-scale integrated circuit, and so instead simpler screening tests are used to distinguish good circuits from circuits with defects or failures. By way of example, this difficulty is illustrated in practice by tests designed to detect breakdown in ultra-thin dielectric layers or by tests designed to measure I.sub.DDQ [which is the current that flows quiescently from the power source (V.sub.DD) of a circuit to ground.] In the course of such testing of particular circuits, devices or structural features, it may be difficult or even impossible to detect a difference between fault-free and defective structures or circuits. In other words, the current or voltage measured during a particular test on a failed structure may be virtually indistinguishable from the corresponding quantity of a good structure. The reason for this is that while the failed region may have a larger current density flowing through it than an equivalent intact and good region, the good region covers much more area, so that, collectively, the total current in the good region is larger, and the characteristic behavior of the failed region is obscured. This becomes an increasing problem for sub-micron-scaled integrated circuits, in which the off-current densities and leakage-current densities are larger than in previous generations of circuits.
Dielectric layers constitute vital elements of a wide variety of electronic components. Thus, for example, silicon dioxide is commonly utilized to form the so-called gate oxide layer of typical metal-oxide-semiconductor (MOS) transistor devices included in an integrated circuit made on a multi-chip wafer. For some high-performance MOS devices, the thickness of the dielectric gate layers may have to be exceedingly small [for instance, only about six nanometers (nm) or less].
Fabricating ultra-thin dielectric layers that meet specified operating criteria is a challenging task. This is particularly true when a large-area dielectric layer must be formed on the entirety of the surface of a wafer or other substrate on which multiple devices are to be made in a batch-fabrication sequence. To minimize the chances that such devices will fail during actual operation, it is advantageous to measure certain characteristics of the dielectric layers of the devices either at some intermediate point in the fabrication sequence or at least before shipping the devices to a customer.
Determining the point at which a dielectric layer breaks down or determining the fraction of devices whose dielectric layers show early breakdown are important ways of assessing the quality of the layer. An actual device or wafer (or a test device or wafer) whose dielectric layer fails to exhibit a prespecified breakdown characteristic would, of course, be rejected for use or utilized as a basis for modifying the fabrication sequence.
As a specific illustrative example, for relatively thick dielectric gate layers (thicker than say about six nm), the breakdown characteristic can usually be adequately measured by any one of a number of standard techniques. Thus, for instance, a voltage applied across such a layer can be periodically ramped up to successively higher values while measuring current flow through the layer. At breakdown, a substantial increase in current flow occurs. In another standard technique, the current through the layer is regularly increased while measuring the voltage across the layer. At breakdown, a substantial decrease occurs in the voltage across the layer. In yet other approaches, either a constant current or a constant voltage is maintained through or across the layer until and subsequent to breakdown. At breakdown, either the voltage decreases (for the constant-current case) or the current increases (for the constant-voltage case). In another early-breakdown screening technique, a voltage higher than some specified operating value is momentarily applied across the layer and the current therethrough is measured. If the current does not exceed a prespecified value, the layer is determined to have not suffered breakdown.
For all of the aforementioned standard testing techniques, distinguishing between the pre-breakdown and breakdown states of a dielectric layer becomes increasingly difficult as the layer gets thinner. Thus, for example, for a silicon oxide layer thinner than about six nm or less, the absolute value of the current through or the voltage across the layer at breakdown may not be statistically different from the corresponding quantity that is measured before breakdown. In such cases, a reliable determination of the breakdown characteristic of the layer being tested is very difficult or even impossible.
In the aforementioned I.sub.DDQ technique for testing integrated circuits, the current, I.sub.DDQ, that flows quiescently from V.sub.DD to ground through a fault-free circuit is measured. This is done, for example, as a voltage V.sub.DD is successively applied to some or all of the power pins of a circuit as different signal voltages are applied, in different sequences, to some or all of the signal pins of the circuit. Each different set of signal conditions applied to the chip is commonly referred to as a test vector. Another realization of the I.sub.DDQ technique comprises, for example, ramping the power supply voltage from zero to V.sub.DD.
For each good circuit being tested, I.sub.DDQ has a characteristic value or waveform, which may be distinct for each different test vector. As heretofore practised, I.sub.DDQ testing relies on the fact that the value of I.sub.DDQ or its waveform in a good circuit will differ in an easily distinguishable way from those in a defective circuit or that certain defects will cause an elevated I.sub.DDQ current. But, as dielectric layers are scaled down in size and/or as other feature sizes of the circuits are significantly reduced, the value or waveform of I.sub.DDQ in a defect-containing circuit is often indistinguishable in practice from the I.sub.DDQ of a corresponding defect-free circuit.
Various suggestions have been proposed for enhancing the reliability of I.sub.DDQ testing as applied to small-feature-size integrated circuits. Thus, for example, on-chip test and sensing circuits designed to measure I.sub.DDQ for just a portion of a chip at a time may extend the utility of the I.sub.DDQ technique. But this modification can interfere with overall circuit performance and require excessive chip area. Also, proposals have been made to modify the manufacturing technology or the design rules in a way to prevent high nominal values of I.sub.DDQ. But such proposals often interfere unacceptably with process and circuit optimization. Further suggestions have been made to measure I.sub.DDQ at ultra-low temperatures. But such measurements may not modify the value or waveform of I.sub.DDQ in a fault-containing circuit in a predictable and consistent manner.
Accordingly, continuing efforts have been directed by workers skilled in the art aimed at trying to devise other ways of measuring breakdown in very thin dielectric layers and other ways of carrying out I.sub.DDQ testing in small-feature-size integrated circuits. It was recognized that such efforts, if successful, would make possible, or at least facilitate, accurate testing of such layers to detect the occurrence of breakdown therein and would also extend the applicability of I.sub.DDQ testing to small-feature-size integrated circuits. In turn, this would provide, for example, a basis for insuring that the breakdown characteristics of very thin dielectric layers included in high-performance devices could be reliably tested and, further, that small-feature-size integrated circuits could be reliably tested by I.sub.DDQ techniques. As a result, the manufacturing yield, cost and long-term operating properties of such devices and circuits could thereby be significantly improved.